Thank you to anyone who has already donated - your generous donations helped make three months of treatment possible.
My brother Nate continues to fight stage IV Hodgkin's lymphoma. He's just 31, with a wife and baby girl. They have no active income (since he's been unable to return to work), no insurance, and cannot afford the treatment he needs. Nate and his family need your help. Please consider a donation, every dollar helps. Thanks.
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diff --git a/firmware/export/rk27xx.h b/firmware/export/rk27xx.h index d1b9758..b66a339 100644 --- a/firmware/export/rk27xx.h +++ b/firmware/export/rk27xx.h @@ -820,7 +820,7 @@ /* LCD controller */ #define AHB1_LCDC 0x186E8000 -#define LCDC_CTRL (*(volatile unsigned long *)(AHB1_LCDC + 0x00)) +#define LCDC_CTRL (*(volatile unsigned short *)(AHB1_LCDC + 0x00)) /* bits 14-31 reserved */ #define ALPHA24B (1<<13) #define UVBUFEXCH (1<<12) @@ -833,7 +833,7 @@ #define RGB_DUMMY(x) (((x)&0x03)<<2) #define LCDC_EN (1<<1) #define LCDC_STOP (1<<0) -#define MCU_CTRL (*(volatile unsigned long *)(AHB1_LCDC + 0x04)) +#define MCU_CTRL (*(volatile unsigned short *)(AHB1_LCDC + 0x04)) #define ALPHA_BASE(x) (((x)&0x3f)<<8) #define MCU_CTRL_FIFO_EN (1<<6) @@ -842,15 +842,15 @@ #define MCU_CTRL_BUFF_START (1<<1) #define MCU_CTRL_BYPASS (1<<0) -#define HOR_PERIOD (*(volatile unsigned long *)(AHB1_LCDC + 0x08)) -#define VERT_PERIOD (*(volatile unsigned long *)(AHB1_LCDC + 0x0C)) -#define HOR_PW (*(volatile unsigned long *)(AHB1_LCDC + 0x10)) -#define VERT_PW (*(volatile unsigned long *)(AHB1_LCDC + 0x14)) -#define HOR_ACT (*(volatile unsigned long *)(AHB1_LCDC + 0x18)) -#define VERT_ACT (*(volatile unsigned long *)(AHB1_LCDC + 0x1C)) -#define HOR_BP (*(volatile unsigned long *)(AHB1_LCDC + 0x20)) -#define VERT_BP (*(volatile unsigned long *)(AHB1_LCDC + 0x24)) -#define LINE0_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x28)) +#define HOR_PERIOD (*(volatile unsigned short *)(AHB1_LCDC + 0x08)) +#define VERT_PERIOD (*(volatile unsigned short *)(AHB1_LCDC + 0x0C)) +#define HOR_PW (*(volatile unsigned short *)(AHB1_LCDC + 0x10)) +#define VERT_PW (*(volatile unsigned short *)(AHB1_LCDC + 0x14)) +#define HOR_ACT (*(volatile unsigned short *)(AHB1_LCDC + 0x18)) +#define VERT_ACT (*(volatile unsigned short *)(AHB1_LCDC + 0x1C)) +#define HOR_BP (*(volatile unsigned short *)(AHB1_LCDC + 0x20)) +#define VERT_BP (*(volatile unsigned short *)(AHB1_LCDC + 0x24)) +#define LINE0_YADDR (*(volatile unsigned short *)(AHB1_LCDC + 0x28)) #define LINE_ALPHA_EN (1<<14) #define LINE_SCALE_EN (1<<13) #define LINE_GBR (1<<12) @@ -859,31 +859,31 @@ #define LINE_RGB_SRC (0<<11) /* bits 0-10 Y_BASE */ -#define LINE0_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x2C)) -#define LINE1_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x30)) -#define LINE1_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x34)) -#define LINE2_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x38)) -#define LINE2_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x3C)) -#define LINE3_YADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x40)) -#define LINE3_UVADDR (*(volatile unsigned long *)(AHB1_LCDC + 0x44)) -#define START_X (*(volatile unsigned long *)(AHB1_LCDC + 0x48)) -#define START_Y (*(volatile unsigned long *)(AHB1_LCDC + 0x4C)) -#define DELTA_X (*(volatile unsigned long *)(AHB1_LCDC + 0x50)) -#define DELTA_Y (*(volatile unsigned long *)(AHB1_LCDC + 0x54)) -#define LCDC_INTR_MASK (*(volatile unsigned long *)(AHB1_LCDC + 0x58)) +#define LINE0_UVADDR (*(volatile unsigned short *)(AHB1_LCDC + 0x2C)) +#define LINE1_YADDR (*(volatile unsigned short *)(AHB1_LCDC + 0x30)) +#define LINE1_UVADDR (*(volatile unsigned short *)(AHB1_LCDC + 0x34)) +#define LINE2_YADDR (*(volatile unsigned short *)(AHB1_LCDC + 0x38)) +#define LINE2_UVADDR (*(volatile unsigned short *)(AHB1_LCDC + 0x3C)) +#define LINE3_YADDR (*(volatile unsigned short *)(AHB1_LCDC + 0x40)) +#define LINE3_UVADDR (*(volatile unsigned short *)(AHB1_LCDC + 0x44)) +#define START_X (*(volatile unsigned short *)(AHB1_LCDC + 0x48)) +#define START_Y (*(volatile unsigned short *)(AHB1_LCDC + 0x4C)) +#define DELTA_X (*(volatile unsigned short *)(AHB1_LCDC + 0x50)) +#define DELTA_Y (*(volatile unsigned short *)(AHB1_LCDC + 0x54)) +#define LCDC_INTR_MASK (*(volatile unsigned short *)(AHB1_LCDC + 0x58)) #define INTR_MASK_LINE (1<<3) #define INTR_MASK_EVENLINE (0<<3) #define INTR_MASK_BUFF (1<<2) #define INTR_MASK_VERT (1<<1) #define INTR_MASK_HOR (1<<0) -#define LCDC_STA (*(volatile unsigned long *)(AHB1_LCDC + 0x7C)) +#define LCDC_STA (*(volatile unsigned short *)(AHB1_LCDC + 0x7C)) #define LCDC_MCU_IDLE (1<<12) -#define LCD_COMMAND (*(volatile unsigned long *)(AHB1_LCDC + 0x1000)) -#define LCD_DATA (*(volatile unsigned long *)(AHB1_LCDC + 0x1004)) +#define LCD_COMMAND (*(volatile unsigned short *)(AHB1_LCDC + 0x1000)) +#define LCD_DATA (*(volatile unsigned short *)(AHB1_LCDC + 0x1004)) -#define LCD_BUFF (*(volatile unsigned long *)(AHB1_LCDC + 0x2000)) +#define LCD_BUFF (*(volatile unsigned short *)(AHB1_LCDC + 0x2000)) /* High speed ADC interface */ #define AHB1_HS_ADC 0x186EC000 #define HSADC_DATA (*(volatile unsigned long *)(AHB1_HS_ADC + 0x00)) diff --git a/firmware/target/arm/rk27xx/lcd-hifiman.c b/firmware/target/arm/rk27xx/lcd-hifiman.c index d98ed5a..6af9132 100644 --- a/firmware/target/arm/rk27xx/lcd-hifiman.c +++ b/firmware/target/arm/rk27xx/lcd-hifiman.c @@ -84,7 +84,7 @@ static void lcd_display_init(void) udelay(40); /* Memmory access setting */ - lcd_write_reg(0x16, 0x48); + lcd_write_reg(0x16, 0x68); /* Setup 16bit mode */ lcd_write_reg(0x17, 0x05); @@ -92,11 +92,11 @@ static void lcd_display_init(void) lcd_write_reg(0x02, 0x00); lcd_write_reg(0x03, 0x00); lcd_write_reg(0x04, 0x00); - lcd_write_reg(0x05, LCD_HEIGHT - 1); + lcd_write_reg(0x05, LCD_WIDTH - 1); lcd_write_reg(0x06, 0x00); lcd_write_reg(0x07, 0x00); lcd_write_reg(0x08, 0x00); - lcd_write_reg(0x09, LCD_WIDTH - 1); + lcd_write_reg(0x09, LCD_HEIGHT - 1); /* Start GRAM write */ lcd_cmd(0x22); @@ -116,6 +116,8 @@ void lcd_init_device(void) void lcd_enable (bool on) { + lcdctrl_bypass(1); + if (on) { lcd_write_reg(0x18, 0x44); @@ -158,6 +160,8 @@ void lcd_update_rect(int x, int y, int width, int height) { int px = x, py = y; int pxmax = x + width, pymax = y + height; + lcd_update(); + return ; lcd_write_reg(0x03, y); lcd_write_reg(0x05, pymax-1); diff --git a/firmware/target/arm/rk27xx/lcdif-rk27xx.c b/firmware/target/arm/rk27xx/lcdif-rk27xx.c index affc49b..9b10e83 100644 --- a/firmware/target/arm/rk27xx/lcdif-rk27xx.c +++ b/firmware/target/arm/rk27xx/lcdif-rk27xx.c @@ -30,6 +30,7 @@ unsigned int lcd_data_transform(unsigned int data) { unsigned int r, g, b; + return data; #if defined(RK27_GENERIC) /* 18 bit interface */ @@ -65,7 +66,7 @@ void lcd_write_reg(unsigned int reg, unsigned int val) lcd_data(val); } -static void lcdctrl_bypass(unsigned int on_off) +void lcdctrl_bypass(unsigned int on_off) { while (!(LCDC_STA & LCDC_MCU_IDLE)); @@ -86,40 +87,24 @@ static void lcdctrl_init(void) * MCU mode * 24b RGB */ - LCDC_CTRL = ALPHA(7) | LCDC_STOP | LCDC_MCU | RGB24B; + LCDC_CTRL = ALPHA(7) | LCDC_STOP | LCDC_MCU; MCU_CTRL = ALPHA_BASE(0x3f) | MCU_CTRL_BYPASS; - HOR_ACT = LCD_WIDTH + 3; /* define horizonatal active region */ - VERT_ACT = LCD_HEIGHT; /* define vertical active region */ + HOR_BP = LCD_WIDTH + 3; /* define horizonatal active region */ + VERT_BP = LCD_HEIGHT; /* define vertical active region */ VERT_PERIOD = 0xfff; /* CSn/WEn/RDn signal timings */ - LINE0_YADDR = LINE_ALPHA_EN | 0x7fe; - LINE1_YADDR = LINE_ALPHA_EN | ((1 * LCD_WIDTH) - 2); - LINE2_YADDR = LINE_ALPHA_EN | ((2 * LCD_WIDTH) - 2); - LINE3_YADDR = LINE_ALPHA_EN | ((3 * LCD_WIDTH) - 2); - - LINE0_UVADDR = 0x7fe + 1; - LINE1_UVADDR = ((1 * LCD_WIDTH) - 2 + 1); - LINE2_UVADDR = ((2 * LCD_WIDTH) - 2 + 1); - LINE3_UVADDR = ((3 * LCD_WIDTH) - 2 + 1); - -#if 0 LINE0_YADDR = 0; - LINE1_YADDR = (1 * LCD_WIDTH); - LINE2_YADDR = (2 * LCD_WIDTH); - LINE3_YADDR = (3 * LCD_WIDTH); + LINE1_YADDR = 1 * LCD_WIDTH/2; + LINE2_YADDR = 2 * LCD_WIDTH/2; + LINE3_YADDR = 3 * LCD_WIDTH/2; LINE0_UVADDR = 1; - LINE1_UVADDR = (1 * LCD_WIDTH) + 1; - LINE2_UVADDR = (2 * LCD_WIDTH) + 1; - LINE3_UVADDR = (3 * LCD_WIDTH) + 1; - - START_X = 0; - START_Y = 0; - DELTA_X = 0x200; /* no scaling */ - DELTA_Y = 0x200; /* no scaling */ -#endif - LCDC_INTR_MASK = INTR_MASK_LINE; /* INTR_MASK_EVENLINE; */ + LINE1_UVADDR = (1 * LCD_WIDTH/2) + 1; + LINE2_UVADDR = (2 * LCD_WIDTH/2) + 1; + LINE3_UVADDR = (3 * LCD_WIDTH/2) + 1; + + LCDC_INTR_MASK = 0; /*INTR_MASK_LINE; INTR_MASK_EVENLINE; */ } /* configure pins to drive lcd in 18bit mode (16bit mode for HiFiMAN's) */ @@ -138,11 +123,11 @@ static void iomux_lcd(enum lcdif_mode_t mode) SCU_IOMUXB_CON |= IOMUX_LCD_D815; } -void lcdif_init(enum lcdif_mode_t mode) +static void dwdma_init(void) { - iomux_lcd(mode); /* setup pins for lcd interface */ - lcdctrl_init(); /* basic lcdc module configuration */ - lcdctrl_bypass(1); /* run in bypass mode - all writes goes directly to lcd controller */ + DWDMA_DMA_CHEN = 0xf00; + DWDMA_CLEAR_BLOCK = 0x0f; + DWDMA_DMA_CFG = 1; /* global enable */ } /* This is ugly hack. We drive lcd in bypass mode @@ -157,7 +142,104 @@ void lcdif_init(enum lcdif_mode_t mode) * Moreover OF sets some bits in IF module registers * which are referred as reseved in datasheet. */ + +/* dwdma linked list struct */ +struct llp_t { + uint32_t sar; + uint32_t dar; + struct llp_t *llp; + uint32_t ctl_l; + uint32_t ctl_h; + uint32_t dstat; +}; + + +/* structs which describe full screen update */ +struct llp_t scr_llp[LCD_HEIGHT]; + + +static void llp_setup(void *src, void *dst, struct llp_t *llp, uint32_t size) +{ + llp->sar = (uint32_t)src; + llp->dar = (uint32_t)dst; + llp->llp = llp + 1; + llp->ctl_h = size; + llp->ctl_l = (1<<20) | + (1<<23) | + (1<<17) | + (2<<1) | + (2<<4) | + (3<<11) | + (3<<14) | + (1<<27) | + (1<<28); +} + +static void llp_end(struct llp_t *llp) +{ + llp->ctl_l &= ~((1<<27)|(1<<28)); +} + + +static void dwdma_start(uint8_t ch, struct llp_t *llp, uint8_t handshake) +{ + DWDMA_SAR(ch) = 0; + DWDMA_DAR(ch) = 0; + DWDMA_LLP(ch) = (uint32_t)llp; + DWDMA_CTL_L(ch) = (1<<20) | + (1<<23) | + (1<<17) | + (2<<1) | + (2<<4) | + (3<<11) | + (3<<14) | + (1<<27) | + (1<<28); + + DWDMA_CTL_H(ch) = 1; + DWDMA_CFG_L(ch) = (7<<5); + DWDMA_CFG_H(ch) = (handshake<<11)|(1<<2); + DWDMA_SGR(ch) = (13<<20); + DWDMA_DMA_CHEN = (0x101<<ch); + +} + + +void create_llp(void) +{ + int i = 0; + + /* build LLPs */ + for (i=0; i<LCD_HEIGHT; i++) + llp_setup(FBADDR(0,i), (void*)(&LCD_BUFF+(i%4)*LCD_WIDTH), &scr_llp[i], LCD_WIDTH/2); + llp_end(&scr_llp[LCD_HEIGHT-1]); +} +void lcdif_init(enum lcdif_mode_t mode) +{ + iomux_lcd(mode); /* setup pins for lcd interface */ + dwdma_init(); + create_llp(); + lcdctrl_init(); /* basic lcdc module configuration */ + lcdctrl_bypass(1); /* run in bypass mode - all writes goes directly to lcd controller */ +} +struct mutex lcd_mtx; void lcd_update() { - lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT); + mutex_lock(&lcd_mtx); + lcdctrl_bypass(1); + lcd_cmd(0x22); + lcdctrl_bypass(0); + + while (!(LCDC_STA & LCDC_MCU_IDLE)); + commit_discard_dcache_range(FBADDR(0,0), 2*LCD_WIDTH*LCD_HEIGHT); + dwdma_start(0, scr_llp, 6); + udelay(100); + + MCU_CTRL=(1<<1)|(1<<2)|(1<<5); + + + while (DWDMA_CTL_L(0) & (1<<27)) + yield(); + + mutex_unlock(&lcd_mtx); } |
